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Espressif Systems /ESP32-C3 /TWAI0 /INT_ENA

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Interpret as INT_ENA

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RX_INT_ENA)RX_INT_ENA 0 (TX_INT_ENA)TX_INT_ENA 0 (ERR_WARN_INT_ENA)ERR_WARN_INT_ENA 0 (OVERRUN_INT_ENA)OVERRUN_INT_ENA 0 (ERR_PASSIVE_INT_ENA)ERR_PASSIVE_INT_ENA 0 (ARB_LOST_INT_ENA)ARB_LOST_INT_ENA 0 (BUS_ERR_INT_ENA)BUS_ERR_INT_ENA

Description

Interrupt Enable Register

Fields

RX_INT_ENA

Set this bit to 1 to enable receive interrupt.
TX_INT_ENA

Set this bit to 1 to enable transmit interrupt.
ERR_WARN_INT_ENA

Set this bit to 1 to enable error warning interrupt.
OVERRUN_INT_ENA

Set this bit to 1 to enable data overrun interrupt.
ERR_PASSIVE_INT_ENA

Set this bit to 1 to enable error passive interrupt.
ARB_LOST_INT_ENA

Set this bit to 1 to enable arbitration lost interrupt.
BUS_ERR_INT_ENA

Set this bit to 1 to enable error interrupt.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/espressif/svd